Improvements in chip manufacturing technology have propelled an astonishing growth of computing systems that are integrated into our daily lives. However, this trend is facing serious challenges, both at device and system levels. At the device level, as the minimum feature size continues to shrink, a host of vulnerabilities influence the robustness, reliability, and availability of embedded and critical systems. Some of these factors are caused by the stochastic nature of the nanoscale manufacturing process (e.g., process variability, sub-wavelength lithographic inaccuracies), while other factors appear because of high operating frequencies and nanoscale dimensions (e.g., RLC noise, on-chip temperature variation, increased sensitivity to radiation and transistor aging). At the other end of the spectrum, these systems are seeing a tremendous increase in software content. Whereas traditional software design paradigms have assumed that the underlying hardware is fully predictable and error-free, there is now a critical need to build a software stack that is responsive to variations, and resilient against emerging vulnerabilities in the underlying hardware.

The interdisciplinary topic of cross layer resiliency spans various disciplines and requires collaboration and cooperation of various communities such as design automation, testing and design for testability, computer architecture, embedded systems and software, validation and verification, fabrication, device, circuits, and systems. Due to the interdisciplinary nature of this work, the study of topics has been distributed over different venues of these communities and therefore we felt a strong need for a dedicated event that can bridge the gap among the disciplines and bring together the experts from various involved communities to address the challenges of cross-layer resiliency.

The objective of this year’s workshop is to continue to build this community of experts interested in multi-level resiliency challenges and solutions and possible paradigm shifts to consider reliability throughout the design flow, from devices to systems and applications. IWCR 2017 will include invited talks by industry experts, short presentations and posters from University researchers (including many whose research was funded by the leading funding agencies in Germany, Japan, UK, and the US), with significant time devoted to in-depth discussions in small breakout groups to identify key technical themes and opportunities for collaborations. We will put more emphasis on posters, in order to facilitate lively discussions.


  • SNU Global Education Center for Engineers, Seoul National University ( Home / Map )
  •  - Driving: Main gate of SNU - Gate 5
  •  - Public transportation: Metro line 2 (Seoul National Univ.) - Bus (5511 or 5513) - Research Institute of Advanced Materials
  •  - Shuttle: Main gate of SNU -College of Engineering


University Hotel

Alternate Accommodation (located within 30 minutes by car to Seoul National University)

Program (PDF)

Confirmed Attendees

  • Nikil Dutt, UC Irvine
  • Joerg Henkel, KIT
  • Ulf Schlichtmann, TU Munich
  • Jongeun Lee, UNIST
  • Yiran Chen, Duke University
  • Hidetoshi Onodera, Kyoto University
  • Soonhoi Ha, Seoul National University
  • Kiyoung Choi, Seoul National University
  • Naehyuck Chang, KAIST
  • Hashimoto, Masanori, Osaka University
  • Aviral Shrivastava, Arizona State University
  • Yongpan Liu, Tsinghua University
  • Kyoungwoo Lee, Yonsei University
  • Jangwoo Kim, Seoul National University
  • Minsoo Ryu, Postech
  • Jihong Kim, Seoul National University
  • Hyunok Oh, Hanyang University
  • Hyungmin Cho, Hongik University
  • Hoeseok Yang, Ajou University
  • Donghwa Shin, Yeungnam University
  • Jaeho Chang, Hyundai Autron
  • Kangwon Lee (VP), SK Telecom
  • Sangyeon Cho (VP), Samsung Electronics
  • Yongin Park (SVP), Samsung Electronics
  • Joonho Um, LG Electronics


General Co-Chairs

  • Naehyuck Chang, KAIST
  • Soonhoi Ha, Seoul National Univ.

Program Co-Chairs

  • Aviral Shrivastava, ASU
  • Kyoungwoo Lee, Yonsei Univ.

Local Arrangement Co-Chairs

  • Yongsoo Joo, Kookmin Univ.
  • Hoeseok Yang, Ajou Univ.

Web Chair

  • Donghwa Shin, Yeungnam Univ.

ISLPED Liaison

  • Yiran Chen, Duke Univ.


  • Youngil Kim, KAIST


Registration fees

  • Full registration: 250 USD
  • Student: 100 USD

Registration site

  • Regonline
  • * Please ​select ​a ​poster ​panel ​from ​the ​merchandise ​items ​when ​the ​registrant ​has ​a ​poster ​presentation. ​ ​


At Sevit Island, Jul. 21. 2017

At GECE, Seoul National University, Jul. 22. 2017

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